The I/O circuitry is fairly simple. The output data is latched in a 74LS175 four bit latch and pushed through half of a 74LS244 buffer. Likewise the input comes in through the other half of the 74LS244 buffer. When reading from input, the input is made active on the data bus for three clock cycles wjile the accumulator is loaded.
Connections to other schematics -
Here is a listing of the connections to other schematics.
|/RESET||Active low reset.|
|/E INPUT||Active low signal to enable input lines on the data buss.|
|OUT LTCH||Active high signal to latch the accumulator into the output latch.|
|D0 through D3||Data bus to accumulator.|
|IN0 through IN3||Inputs from the outside world.|
|OUT0 through OUT3||Outputs to the outside world.|
Send questions and comments to WireHead@GalacticElectronics.com
(c) Jon Qualey, December 2006
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