The clock is a 74LS624. This is a TTL VCO. The 74LS124 is similar and the 74LS629 is a dual VCO. I chose this IC because it has an enable input and two outputs, one output being the complement (inverted) of the other. When the the VCO is disabled (as it is in reset mode), there is no signal output. When the VCO is enabled, the first clock cycle is guaranteed to be %100 duty cycle. I'm using the inverted output to clock the CPU. This way, when reset is removed, the clock out is low for half a clock cycle. I believe this allows everything else in the CPU circuit to settle before program execution begins.
There is a three position switch to select one of three clock speeds. These clock speeds are 10Hz, 400Hz and 165kHz. The two lower speeds are meant to be used for debugging programs. The 10Hz speed allows the accumulator, flag, address and instruction values to be observed during program execution. It is difficult to verify that the CPU functions properly at 165kHz but I assume that it would.
The 74LS624 can be difficult to acquire these days. I don't think any of the TTL VCOs mentioned are in production any more. I purchased 74LS624s from a surplus outlet. I'm sure there are other oscillator / clock ICs available with characteristics similar to the 74LS624.
A 74LS93 is used for sequencing the micro-instruction logic in the 2716 EPROMs. The code for each instruction is four, 16 bit words. A program is composed of instructions. However, the CPU needs to know how to execute these instructions and this is called micro-instruction logic, or micro-instruction code. This code is stored in the EPROMs. Each time a program instruction is executed, four of these 16 bit words of micro-instruction code is executed. The outputs of the EPROMs are used to control the switching in the CPU and this will be discussed more later.
The first group of micro-instruction code, at addresses 0 through 3, is the program instruction fetch code. The fetch instruction retrieves the program instruction from program memory. The fetch instruction is always executed before every program instruction to fetch the instruction from program memory. The fetch instruction should never be called from a program, it is to be used only internally by the CPU. The remaining CPU instructions are located at addresses 4 through 7, 8 through 11, etc...
When the ripple counter (74LS93) counts, the two least siginificant bits, A and B, which are connected to the address lines A0 and A1 of the EPROMs, cycle through one of the four, 16 bit word micro-instructions. Counts 0 through 3 execute the fetch instruction. During the next four counts, the C output of the counter is high. The C output is connected to a group of four AND gates. This enables any code on the inputs of the AND gates to be present on the EPROM address lines A2 through A5 (they are otherwise 0). The code at the inputs of the and gates (shown INS0 through INS3 on the schematic) is the program instruction code from program memory. The program instruction codes are used as an offset to select the proper group of four, 16 bit micro-instruction codes.
So, to summarize, the first counts (0 - 3) executes the fetch instruction to fetch the program instruction and the next counts (4 - 7) execute the program instruction. The process is repeated again at counts 8 - 11 and 12 - 15. Since the D output of the counter isn't used, it doesn't matter what value it holds, the outputs A, B and C cycle the same way.
The outputs of the EPROMs are connected to various ICs in the CPU circuit. These are count up, count down and load inputs on the 74LS193 being used as an accumulator, latch inputs on various 74LS175 latches and so-on. Some of these lines are active high and need to be kept in the low state until needed. This brings us to why there are inverters on many of the EPROM outputs.
I am probably using the 2716 EPROMs in a way they are not supposed to be used. I chose the 2716 because there many of them on the surplus market and can be salvaged from old discarded PC peripherals, as I have done. Anyway, when an output line on the 2716 is held low for more than one count cycle (by containing zeros), there is a glitch on the output when the address is changed. This glitch looks like this on an oscilliscope -
Of course these glitches cause swithing in the CPU when it is not desired. The glitches are not present when the EPROM output is held in a high state. So, the solution to the problem is to keep all EPROM outputs high. When an output needs to be low for one clock cycle, an inverter is put on the output.
I emphasize "one clock cycle". Sometimes one of the outputs needs to be low for three clock cycle (during memory and register loads to the accumulator). Holding the EPROM output low for three clock cycles re-introduces the glitches. The solution I used for this problem are flip-flops. 74LS74 flip-flops are clocked on and off producing a glitch free, three cycle low output. An alternate arrangement for the flip-flops would be this -
The reason I show this is because I had a glitching problem with one of the flip-flops causing it to switch irregularly. I had to put a 200pf capacitor between the flip-flop output and ground to aleviate the problem (and this will limit clock speed). I believe this may be cause by the /Q output on the flip-flop, which is connected back to the D input, is also used for output.
Connections to other schematics -
Here is a listing of the connections to other schematics.
|RESET||Active high reset.|
|/RESET||Active low reset.|
|INS0 through INS3||Instruction code from program memory.|
|LTCHFLAG||Active high signal to latch the flags into the flags register.|
|/WR||Active low signal to write the accumulator to a register.|
|LTCH REG||Active high signal to latch the register address into the register address latch.|
|/DEC ACC||Active low signal to decrement the accumulator.|
|/INC ACC||Active low signal to increment the accumulator.|
|/LD ACC||Active low signal to load the accumulator.|
|INC PC||Active high signal to increment the program counter.|
|LTCH INS||Active high signal to latch the program instruction into the instruction latch.|
|/E INPUT||Active low signal to enable input lines on the data bus.|
|/E INS DATA||Active low signal to enable program data on the data bus.|
|/RD||Active low signal to enable the selected register on the data bus.|
|OUT LTCH||Active high signal to latch the accumulator into the output latch.|
|/RESTART||Active low signal to reset the program counter.|
|JMPG||Active high signal to latch the segment register when the greater than flag is set.|
|JMPE||Active high signal to latch the segment register when the equal flag is set.|
|JMPL||Active high signal to latch the segment register when the less than flag is set.|
Micro-instruction code -
Here is the micro-instruction code listing for the two EPROMs -
ROM 0 is the one at the top of the schematic.
|ADDRESS||ROM 0||ROM 1|
Details of the micro-instruction code is shown here -Micro-instruction Code Detail
Send questions and comments to WireHead@GalacticElectronics.com
(c) Jon Qualey, December 2006
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