This is the arithmetic logic unit of the CPU. It doesn't do a whole lot of arithmetic. The accumulator can be incremented and decremented. Also, the accumulator can be compared to one of the registers or a literal value in the program code.
An instruction is composed of a four bit instruction code and optional four bits of program data. This program data can be loaded into the accumulator or may be compared to the accumulator. Data cannot be written back to program memory at runtime.
The accumulator -
The accumulator is a 74LS193 which is a four bit, up-down counter that can be loaded with data. Any data loaded from program memory or from input passes through the accumulator first. Also, the four registers are read from and written to by the accumulator. When the accumulator is loaded, the source of data is enabled on the data bus (they are all tri-state devices) for three clock cycles. The accumulator is loaded on the second (middle) clock cycle. This is done to ensure the inputs at the 74LS193 are stable when the data is loaded.
The registers -
The registers are implemented with a 74LS670, which is similar to the 74LS170 but has tri-state outputs. This is a 4x4 register file (four, 4 bit words). The address of the individual registers are held in a 74LS175 four bit latch. The contents of the register address latch are written to by the accumulator with the REG instruction. The input and output addresses are independent of each other. When a register is read, the register output is activated on the data bus while the accumulator is loaded. The register addresses are formated as follows -
Four bit word : RRWW WW - Write address. RR - Read address. 00 - Register A 01 - Register B 10 - Register C 11 - Register D
Comparing the accumulator and flags -
The accumulator can be compared to a literal value in program memory or a register. When a literal value is compared, the program data memory (2114) is activated on the data bus for three clock cycles while the flags latch is set. Likewise, to compare the accumulator to a register, the register is activated on the data bus for three clock cycles while the flags latch is set.
A 74LS85, a four bit magnitude comparator is used for making the comparison. It has three outputs, less than, equal and greater than. This gives us three flags. The output of the 74LS85 is latched in a 74LS175 latch when a CMPL or CMPR instruction is executed. A group of AND and OR gates are used to execute a jump when a given flag is set. The LTCH SEG output of the last OR gate will load the program address segment latch with the accumulator contents when it goes high. The JMPL, JMPE and JMPG connections to the AND gates determine which flag to check for a jump. If the flag is set, the segement register is loaded causing program execution to jump to another program segement.
Connections to other schematics -
Here is a listing of the connections to other schematics.
|RESET||Active high reset.|
|/RESET||Active low reset.|
|INS0 through INS3||Instruction code from program memory.|
|LTCHFLAG||Active high signal to latch the flags into the flags register.|
|/WR||Active low signal to write the accumulator to a register.|
|LTCH REG||Active high signal to latch the register address into the register address latch.|
|/DEC ACC||Active low signal to decrement the accumulator.|
|/INC ACC||Active low signal to increment the accumulator.|
|/LD ACC||Active low signal to load the accumulator.|
|INC PC||Active high signal to increment the program counter.|
|LTCH INS||Active high signal to latch the program instruction into the instruction latch.|
|/E INPUT||Active low signal to enable input lines on the data bus.|
|/E INS DATA||Active low signal to enable program data on the data bus.|
|/RD||Active low signal to enable the selected register on the data bus.|
|OUT LTCH||Active high signal to latch the accumulator into the output latch.|
|/RESTART||Active low signal to reset the program counter.|
|JMPG||Active high signal to latch the segment register when the greater than flag is set.|
|JMPE||Active high signal to latch the segment register when the equal flag is set.|
|JMPL||Active high signal to latch the segment register when the less than flag is set.|
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(c) Jon Qualey, December 2006
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